1. Field of the Invention
The present invention relates to a phase lock loop circuit using a sample and hold switch circuit which can maintain a stable operation in spite of input data which includes many consecutive identical bits (0s or 1s ) in a data transmission system, or the like.
2. Description of Related Art
Phase lock loop circuits play an important role as a basic circuit element in data transmission systems such as communication networks or computer networks. They are employed for examples, in repeating circuits or terminating circuits of a data transmission system as a timing signal recovery circuit for generating a clock signal from data, or as a skew timing control circuit for adjusting timings between data and clock signals.
FIG. 1 shows a conventional circuit which employs a phase lock loop circuit for deciding data and recovering a timing signal (clock signal). In this figure, the reference numeral 1 designates a decision circuit for detecting data, 2 designates a doubler, 3 designates a voltage controlled oscillator (VCO), 4 designates a phase comparator, 5 designates a low-pass filter (LPF), 6 designates a data input terminal, 7 designates a data output terminal, and 12 designates a timing signal (clock signal) output terminal.
The input data 6A applied to the data input terminal 6 is doubled in frequency by the doubler 2, and its output signal 2A is compared with the VCO output 3A by the phase comparator 4. The output 4A of the phase comparator 4 is converted to a DC (direct current) voltage 5A by the low-pass filter 5, and is fed back to all oscillation frequency control terminal of the VCO 3. Thus, the timing signal (clock signal) in phase with the input data 6A is recovered. The decision circuit 1 detects the logic state of the input data 6A using the clock signal, and outputs the detected data through the data output terminal 7.
FIG. 2 schematically illustrates operational waveforms of various portions of the conventional circuit of FIG. 1 during the phase lock process. The input data 6A to the data input terminal 6, the output data 7A from the data output terminal 7, the doubler output 2A of the doubler 2, the VCO output 3A of the VCO 3, the phase compared output 4A of the phase comparator 4, and the low-pass filter output 5A of the low-pass filter 5 are shown in (A)-(F) of FIG. 2, respectively. The phase compared output 4A from the phase comparator 4 is illustrated in terms of (a) phase lead, (b) in phase, and (c) phase lag, and the low-pass filter output 5A is illustrated in terms of a phase lead and a phase lag.
The operation of the conventional circuit of FIG. 1 will be described referring to FIG. 2. The input data 6A is converted by the doubler 2 into the waveform 2A as shown in (C) of FIG. 2. This waveform 2A is compared with the VCO output 3A by the phase comparator 4. When the phase of the VCO output 3A leads that of the doubler output 2A, the phase comparator 4 produces a pulse train including positive pulses whose width corresponds to the phase difference as shown in (a) of (E). Conversely, when the phase of the VCO output 3A lags behind that of the doubler output 2A, the phase comparator 4 generates a pulse train including negative pulses as shown in (c) of (E), and when the phases of the two agree, no pulse is generated as shown in (b) of (E).
Subsequently, the compared output 4A from the phase comparator 4 is passed through the low-pass filter 5, and is converted into a continuous low frequency signal as shown in (F). The low-pass filter output 5A is negatively fed back to the oscillation frequency control terminal of the VCO 3, and the operation of the system converges on the basis of the feedback logic in such a manner that the phase difference between the doubler output 2A and the VCO output 3A becomes minimum. As a result, the VCO output 3A (that is, the timing signal, or the clock signal) in synchronism with the input data 6A is obtained. The decision circuit 1 is a functional circuit that detects the logic state of the input data 6A by using the clock signal recovered as described above. For example, detecting the input data 6A using the falling edges of the clock signal will give the output waveform 7A as shown in (B) of FIG. 2 as a result of deciding the logic state.
The conventional circuit of FIG. 1, however, has a problem in that the phase lock loop circuit becomes unstable for consecutive identical bits, and may fall into all unlocked state depending on the number of consecutive identical bits. The consecutive 0s of the input data 6A in (A) of FIG. 2 illustrates this. In this case, since the output 2A of the doubler 2 becomes zero as shown in (C), the phase comparing operation between the output 2A and the VCO output 3A cannot be carried out. Thus, the phase compared output 4A from the phase comparator 4 will be independent of the phase difference between the doubler output 2A and the VCO output 3A during this interval.
Therefore, the output 4A of the phase comparator 4 is not obtained as shown in (a) and (c) of (E) of FIG. 2. Therefore, the phase lock loop circuit operates in such a manner that it automatically returns to its initial state, in which no input data is applied to the input terminal 6. In addition, the low-pass filter output 5A is also pulled back to its initial state during the consecutive 0s as shown in (F) of FIG. 2. Accordingly, the oscillation frequency of the VCO 3 also returns to its initial value. As a result, the conventional phase lock loop circuit cannot maintain the phase locked state for input data including a long consecutive identical bit state.
Generally speaking, an increasing resistance to the consecutive identical bit state can be achieved as the time constant of the low-pass filter 5 is increased. An excessive time constant, however, causes a reduction in the open-loop gain of the phase lock loop circuit, which is the tradeoff with the readiness of being pulled into the locked state at the start of operation of the phase lock loop circuit. For this reason, this method of increasing the time constant cannot be practically applied to such a system that handles input data including several tens of consecutive identical bits. Moreover, a low-pass filter having a large time constant is bulky, and this presents a problem in that it is difficult for a phase lock loop circuit including such a low-pass filter to be integrated into a monolithic integrated circuit. Furthermore, the conventional circuit of FIG. 1 presents a problem in that it sometimes cannot detect the data at the optimum point (the center of individual bits) because the phase relationship between the timing signal of the decision circuit 1 and the input data 6A is impaired owing to the absolute delay due to lines or wire. In particular, in a high-speed circuit, this mistiming of detection will increase an error rate due to faulty operation, which presents another problem.
FIG. 3 shows another circuit for recovering data and a timing signal (clock signal) by using a conventional phase lock loop circuit. This circuit differs from the conventional circuit of FIG. 1 in that it does not include the doubler 2, and that it performs the phase comparison between the input and output of the decision circuit 1 rather than between the doubler output 2A and the VCO output 3A. The other portions are the same as those of FIG. 1.
FIG. 4 schematically illustrates the operational waveforms of various portions of the conventional circuit as shown in FIG. 3 during the phase lock process. FIG. 4 differs from FIG. 2 in that it does not include the doubler output 2A, and the other signals 6A, 7A, 3A, 4A and 5A are similar to those of FIG. 2. The operation of the conventional circuit of FIG. 3 will be described below with reference to FIG. 4.
First, it should be noticed that the phase of the output data 7A lags behind that of the input data 6A by half a period under the condition that the logic state of the input data is decided by an optimum clock signal. The conventional circuit of FIG. 3 uses this, and the phase comparator 4 detects whether the phase difference between the input data 6A and the output data 7A is maintained at half the period of the data, and outputs the phase compared output 4A. For example, when the phase of the output data 7A of the decision circuit 1 leads that of the half-period delayed input data 6A as shown in (A) and (B) of FIG. 4, a pulse train consisting of positive pulses whose width corresponds to the phase difference is generated as shown in (a) of (D) of FIG. 4. In contrast, when the phase of the output data 7A lags behind that of the half-period delayed input data 6A, a pulse train consisting of negative pulses is generated as shown in (c) of (D), and when there is no phase difference between the two, no pulse is generated as shown in (b) of (D).
The subsequent operation is similar to that of the conventional circuit of FIG. 1. More specifically, the output 4A of the phase comparator 4 is converted to a low frequency signal through the low-pass filter 5 as shown in (E) of FIG. 4, and the low-pass filter output 5A is negatively fed back to the oscillation frequency control terminal of the VCO 3. Thus, the phase lock loop system operates on the basis of the feedback principle so that the phase of the VCO output 3A will converge to such a value that the phase difference between the input and output of the decision circuit 1 becomes half a period. As a result, the VCO output (that is, the timing signal or the clock signal) 3A in synchronization with the input data 1A is obtained. Moreover, since the phases are compared between the input and output of the decision circuit 1, the decision of the input data is always carried out at the optimum point.
The phase lock loop circuit of FIG. 3 is superior to that of FIG. 1 in that it can automatically control the relationship between the input data 6A and the clock signal 3A (that is, it can achieve automatic timing skew adjustment). The circuit, however, still has a problem in that it cannot maintain its stability for input data including consecutive identical bits, because the output of the phase comparator 4 takes a level independent of the phase difference.
FIG. 5 shows results of a circuit simulation about the conventional circuit of FIG. 3. In this figure, the axis of abscissas represents time (nsec), and the axis of ordinates represents voltage, and the waveforms of the output data 7A and the clock signal 3A are illustrated. Enlarged waveforms of sections W1 and W2 in (A) of FIG. 5 are shown in (B) and (C) of FIG. 5, respectively. It is assumed in the circuit simulation that the decision circuit 1 comprises ordinary D flip-flops, the phase comparator 4 is a multiplier type, the low-pass filter 5 is composed of a resistor and a capacitor, and the VCO is a multivibrator type. It is further assumed that the transmission rate of the input data is 2.5 Gb/s, and transistors constituting the circuit are an Si bipolar transistor whose high cutoff frequency is about 30 GHz. The simulation was carried out using the analog simulator program SPICE on a work station.
The output waveforms 7A and 3A illustrate changes caused by 63 consecutive 0s inputted after the phase lock loop system is pulled into the stable state (phase locked state) by the input data consisting of alternate 1s and 0s. If the phase locked state is maintained during this 63 consecutive 0s, 63 clock pulses will be outputted during this interval. Actually, however, 64 clock pulses are generated during the first interval as shown in FIG. 5 Part B, and 69 clock pulses are generated during the third interval as shown in FIG. 5 part C. This indicates that the phase locked state is broken by the consecutive identical bits.
FIG. 6 shows another conventional circuit for recovering data and a time signal (clock signal) without employing a phase lock loop circuit. In this figure, the reference numeral 16 denotes a tuning circuit, and 17 denotes an amplitude limitation amplifier. The other components are the same as those of FIG. 1. The tuning circuit 16 tunes in the clock signal frequency so that it recovers the clock from the input data. The amplitude limitation amplifier 17 outputs a signal of a constant amplitude in spite of changes in the amplitude of the input data.
FIG. 7 shows operational waveforms of the conventional data and timing signal recovery circuit as shown in FIG. 6. This figure illustrates waveforms of the input data 6A, the output data 7A, the output 2A of the doubler 2, the output 16A of the tuning circuit 16, and the output 17A of the amplitude limitation amplifier 17. The operation of the conventional circuit of FIG. 6 will be explained with reference to FIG. 7.
First, the input data 6A is doubled in frequency by the doubler 2. The output 2A of the doubler 2 is passed through the tuning circuit 16, and the clock signal component is recovered as the output 16A. The amplitude limitation amplifier 17 amplifies the output 16A, and outputs the signal 17A whose amplitude is constant as shown in (E) of FIG. 7. The output 17A is used as the clock signal of the decision circuit 1 which carries out the logic detection of the input data 6A. A sufficiently high Q of the tuning circuit 16 makes it possible to maintain the clock signal component even during a consecutive identical bits as shown in (D) of FIG. 7 although the amplitude will be gradually reduced during resonance. Amplifying the output 16A such that its amplitude becomes constant by the amplitude limitation amplifier 17 enables the clock signal to be maintained during the consecutive identical bits.
As the tuning circuit 16 having a high Q of above several thousands, a coaxial resonator or a surface acoustic wave (SAW) filter is generally used, which operates stably for consecutive identical bits of more than 100 bits. Therefore, this circuit is more widely used as the data and timing signal recovery circuit than the above-described two conventional circuits employing a phase lock loop circuit. Considering a monolithic integration of this circuit, however, a new problem arises in that an external component must be used as the tuning circuit 16 because no existing technique can implement a monolithic integration of a high Q circuit. As a result, a fully monolithic integrated circuit cannot be realized, which makes it difficult to provide a small, highly reliable, low cost circuit. Furthermore, all amplitude limitation amplifier 17 of a higher gain is required in order to realize a larger resistance to identical consecutive bits, and this makes it difficult to implement a circuit with stable operation. In particular, there is a problem in that such a circuit becomes more difficult to realize as all increasing resistance to consecutive identical bits at a higher frequency is required.
In summary, the conventional phase lock loop circuit used as the data and timing signal recovery circuit cannot provide a correct phase compared output during a consecutive identical bit interval. This presents a problem in that the increasing number of consecutive identical bits will make the phase lock loop circuit more unstable, and sometimes cause pulling out of synchronism. In addition, a conventional circuit not using a phase lock loop circuit has limits in implementations of a small, highly reliable, low cost circuit because a fully monolithic integrated circuit cannot be realized with such a circuit.